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8-Channel FEC Tests of 400-GbE Transceivers

Anritsu MP1900 PAM405 February 2020 – Anritsu Corporation is now supporting FEC tests of 400-GbE and next-generation 800-GbE QSFP-DD and OSFP transceivers by adding PAM4 PPG 8ch synchronous/FEC pattern-generation functions to the company’s Signal Quality Analyzer-R MP1900A series.

FEC is being adopted at data centers using PAM4 to implement faster and larger-capacity 400-GbE, etc., communications with assured quality. In addition, there is also active development of 4- and 8-multilanes as well as PAM4 technologies. As a result, transmission quality tests for QSFP-DD, OSFP, etc., optical modules urgently need techniques to confirm the degree of error correction using multilane FEC patterns with added jitter and ISI stress. Moreover, such measurements require a signal source for accurate control of the 8 synchronized channels and the phase and patterns between channels.

The Signal Quality Analyzer-R MP1900A series Pulse Pattern Generator all-in-one BERT supports both generation of 400-GbE PAM4-signal multichannel FEC patterns and Jitter Tolerance measurements. As well as supporting 1ch and 4ch patterns, 8ch pattern synchronization and FEC pattern generation functions have been added to this unique high-speed PAM4 BERT, supporting 8-lane transceivers for 400-GbE communications.

Outline of Stress Tests using MP1900A FEC Patterns

Since accurate FEC tests are impossible using methods adding jitter stress to just one out of 8 lanes, it is necessary to test by adding jitter stress to all synchronized lanes. Consequently, the Anritsu MP1900A series supports generation of 8ch synchronized FEC patterns defined by the 400GBASE-LR8/FR8*5 standard, as well as error insertion, and jitter and ISI stress functions using the MU196020A PAM4 PPG Multimode with the Inter-Module Sync, FEC Pattern Generation, Emphasis, and Adjustable ISI options. 8ch stressed signals synchronized using these functions are transmitted to QSFP-DD, etc., transceivers to implement more-reliable, high-reproducibility FEC tests by analyzing the results after error correction.

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