News - Board and System Test

Optimized Test and Debug Tools for the latest Multicore SoCs

16 September 2014 – In parallel to Freescale’s presentation of its latest Qorivva derivates, PLS Programmierbare Logik & Systeme now provides system developers with its Universal Debug Engine (UDE) for the multicore System-on-Chips (SoCs) MPC5746M, MPC5777M, MPC5748G, MPC5746C, MPC77xK and MPC574xP. PLS is one of the first tool suppliers to offer development tools specifically optimized for the features and functions of these multicore SoCs.

Several already prepared configurations of the UDE ensure an uncomplicated first connection as well as a fast and reliable programming of the flash memory which is integrated in various sizes on the Qorivva devices. With help of the UDE’s multicore/multiprogram loader, the relevant program codes and the corresponding debug information can be assigned to individual cores in a flexible way. In addition, the heterogeneous structure of the SoCs — that, besides the main cores, depending on the type, can contain further programmable units such as a Generic Timer Module (GTM) or a Hardware Security Module (HSM) — is optimally supported. By core-specific grouping of debugger windows (optionally with automatic fade in and fade out depending on the active core as well as different coloring) UDE-users are provided with an optimal overview of their complete multicore system in just one single consistent user interface.

Control of the diverse cores by the debugger is carried out via the so-called multi-run control function, which enables an almost synchronous start and stop of the various cores by making use of debug logic integrated on the respective chip. In addition, debugging is simplified by the multicore breakpoints newly implemented in the UDE. With their help, in shared code a simultaneously acting breakpoint for all cores can be very easily set. Data breakpoints allow the recognition of read and/or write accesses to a variable. A certain expected value can even be optionally taken into account.

In the optimization of the UDE, particular attention was also given to efficient support of all possible trace variants. While data transfer takes place via a conventional parallel port with the types MPC5746C, MPC5748G and MPC574xP, a serial high-speed interface that is based on the Aurora protocol is available for the MPC5746M, MPC577xK, MPC5777M and MPC574xP devices. This offers type-dependent four or two lanes each with 1.25 Gbps data transfer rate, which are processed without limitations by the Aurora trace pod of the Universal Access Device (UAD) 3+. Furthermore, for parallel trace, users can make use of a pod with up to 32-bit recording width.

The various device-specific optimizations of the UDE are particularly valuable, among others, with the Qorivva derivates MPC5746M and MPC5777M that were specifically designed for motor controls. With these SoCs, Freescale also integrated a few KByte trace memory on the production chip. This trace memory, together with a Signal Processing Unit (SPU) also integrated on the chip, is ideally suited for troubleshooting. The SPU, which can usually only be laboriously programmed at register level, can be very easily configured for various measurement tasks with the Universal Emulation Configurator (UEC), which is optionally available to the UDE from PLS. Besides control of the trace recording, the underlying state machine model also allows the definition of complex breakpoints with sequencer logic.

www.pls-mc.com/

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