This website uses cookies to implement certain functions. If you use this website you agree to our Privacy Policy.
News and Information about the Test of Electronics in Research & Design, Production, Maintenance, and Installation.  

Newsletter

Register to our newsletter
Every two weeks -
all news at a glance
captcha 

News - Board and System Test

XJTAG DFT for Mentor Graphics PADS

XJTAG Mentor20 March 2017 – XJTAG developed a free software for PADS Schematic Design which will significantly increase the Design for Test and Debug capabilities of the schematic capture and PCB design environment. The XJTAG DFT Assistant comprises the XJTAG Chain Checker and the XJTAG Access Viewer.

Printed circuit boards (PCBs) are increasingly densely populated and access to pins under many packages, such as Ball Grid Array (BGA), is virtually impossible. JTAG was designed to solve the problem of access and so it is now vitally important to get the JTAG chain right at the design stage. Failure to identify and fix design errors at an early stage can result in a board re-spin and a costly delay to a project. XJTAG DFT Assistant helps validate correct JTAG chain connectivity, through full integration with the PADS schematic capture environment.

“PADS products now include the XJTAG DFT Assistant that provides engineers with a free, easy to use interface to check if JTAG chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced,” said Jim Martens, Product Marketing Manager, PADS Solutions Group. “By detecting and correcting these faults earlier, companies do save both time and money. This software is free for PADS users of VX.2.1 or higher and can be downloaded from www.xjtag.com/pads.”

The XJTAG DFT Assistant comprises of two key elements; the XJTAG Chain Checker, and the XJTAG Access Viewer.

 XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected Test Access Ports (TAPs). A single connection error would inhibit an entire scan chain from working. XJTAG Chain Checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.

 XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets that don’t have any JTAG access on the schematic.

While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from the PADS schematic capture environment to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware, as soon as it’s available. This provides a vital new capability to electronic engineers everywhere.

www.xjtag.com/



Related Articles:

No related articles found


Upcoming Events

EMV 2018
Duesseldorf (Germany)
20 to 22 February 2018
Mobile World Congress 2018
Barcelona (Spain)
26 February to 01 March 2018
Embedded World 2018
Nuremberg (Germany)
27 February  to 01 March 2018

Social Media

twitter_follow_420x50px