News and Information about the Test of Electronics in Research & Design, Production, Maintenance, and Installation.  

Newsletter

Register to our newsletter
Every two weeks -
all news at a glance

General T&M

Enhanced JTAG/Boundary Scan Test Coverage

10 October 2011 - A new model-based test methodology for ASSET InterTech's ScanWorks platform for embedded instruments extends non-intrusive Boundary Scan (JTAG) test coverage to devices that previously could not be tested or programmed with Boundary Scan.

With the new modeling method, referred to as the ScanWorks Component Action, an engineer can quickly describe certain devices like system monitors on the I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface) buses, switches, power managers, LEDs (light emitting diodes), clocks, data converters and memories that do not typically conform to the IEEE 1149.1 boundary-scan (JTAG) standard. When a model has been created in the Component Action, it can be placed in a library so that it can be re-used and automatically included in any number of boundary-scan tests for different circuit boards or platforms. Previously, a great deal of tedious manual effort was required before these devices could be tested or programmed with a boundary-scan test tool.

"The ScanWorks Component Action has a new graphical user interface which simplifies non-boundary-scan device modeling as well as test and bus definition," said Kent Zetterberg, ASSET's product manager for ScanWorks boundary-scan test tools. "It's a very powerful tool that saves test engineers a tremendous amount of time because many of these devices are used over and over again in new designs. Once the model is generated, it can be dropped into any new test that ScanWorks generates."

Component Action models of non-boundary-scan devices will be added to the constantly growing ScanWorks online model library. The library currently contains tens of thousands of models for boundary-scan devices and other types of non-boundary-scan devices, including memories like NOR/NAND flash, EEPROM, RAM, SRAM, DRAM, DDR SDRAM and others. All of these models significantly shorten the time engineers spend developing tests by enabling automatic test pattern generation (ATPG) within ScanWorks.

www.asset-intertech.com


Upcoming Events

Southern Manufactruing 2015
Farnborough (UK)
10 to 12 February 2015
Embedded World 2015
Nuremberg (Germany)
24 to 26 February 2015

Tag Cloud

Social Media

linkedin_follow_420x50px
 
twitter_follow_420x50px